1. Field of Invention
This invention pertains to the simulation or emulation on a processor of a simulating computer system of programmed instructions prepared for a processor of a simulated computer system.
2. Related Art and Other Considerations
Computer systems have processors which recognize and execute coded instructions, e.g., software, in order to perform activities and thereby obtain desired results and/or outputs. To be executed by any particular processor, a coded instruction must be interpreted or otherwise reducible for expression as an instruction belonging to a predefined instruction set which is native to the processor.
Differing types of processors can (and typically do) have differing instruction sets. Yet, it is often necessary to execute instructions prepared or written for a first type of processor (herein referred to as the target processor) on a second type of processor (herein referred to as the host processor). That is, circumstances may require that instructions coded in accordance with an instruction set of the target processor be executed on the host processor, although the host processor utilizes a different instruction set than the target processor. Such can occur, for example, when it is necessary or desirable for the host processor to simulate or emulate the target processor, e.g., in order to test software written for the target processor.
When a host processor serves to emulate a target processor, the host processor stores the software written for the target processor (i.e., the target instructions) in a memory. The host processor executes an emulation program, which includes both a translation process and a translated-instruction execution process. In connection with the translation process, the emulation program decodes each target instruction to determine its type (e.g., an "add registers" instruction, a "move" instruction, etc.). For the translation process, the host processor has access elsewhere in memory to translation code. The translation code is written in accordance with the instruction set of the host processor. For each type of target instruction, the translation code includes a series of host instructions which enable the host processor to generate emulation code (in accordance with the host instruction set). The emulation code enables the host processor to perform equivalent actions as required by the target instruction.
In simulation/emulation situations such as that summarized above, it has been known to use a jump table. In essence, the jump table contains pointers to the series of host instructions in the translation code which generate the emulation code corresponding to the target instruction. That is, when the emulation program decodes a target instruction to determine its type, for that particular target instruction type the jump table has a pointer to the particular translation code which generates emulation code in terms of the host instruction set. Jump tables are described, e.g, in MacGregor's International Patent Application PCT/GB87/00202, "ARRANGEMENT FOR SOFTWARE EMULATION".
Jump tables can interject delay and increase memory requirements. Accordingly, avoiding jump tables is described in the prior art. See, for example, Davidian's International Patent Application PCT/US94/03911, "METHOD FOR DECODING GUEST INSTRUCTIONS FOR A HOST COMPUTER", which decodes guest instructions based on direct access to instructions in an emulation program.
Simulation and emulation are particularly important in modeling complex processing systems such as those employed in the telecommunications industry. Such processing system typically have an instruction processor which executes blocks of code. The blocks of code are stored in a memory known as the program store. The instruction processor must also be capable of handling signals. As used herein, a "signal" is a message sent from one block of code to another. The signal comprises both a signal header and a signal body. The signal header includes an identifier of the sending block and the recipient block, as well as a signal number or type. The signal body includes data which is to be utilized by the recipient block in the execution of the signal.
When such a processing system as described in the preceding paragraph is considered a target processor for emulation on a host processor, an efficient method is necessary for translating the blocks of code and the signals. Moreover, should the target processor utilize an instruction set having non-uniform instruction length, coordinating target instructions to jump table locations becomes problematic.
What is needed, therefore, and an object of the present invention, is an emulation/simulation system that is efficient, compact, and able to both handle signals and target instructions of non-uniform length.